Method and apparatus for transferring data on a voltage biased data line

ABSTRACT

Method and apparatus for transferring data on a voltage biased data line are disclosed. In one embodiment, there is provided a bus interface for controlling a differential bus having a differential data line that includes a first bus line and a second bus line. The bus interface includes a bus controller circuit, an impedance network, and a controllable biasing circuit. The bus controller circuit is coupled to the differential bus and is configured to (i) control transfer of data across the differential bus, and (ii) generate a biasing control signal prior to data transfer on the differential data line. The impedance network is coupled to the first bus line and the second bus line and is configured to substantially match a characteristic impedance of the differential data line. The controllable biasing circuit is coupled to the differential data line and is configured to (i) develop a differential biasing voltage between the first bus line and the second bus line, and (ii) to remove the differential biasing voltage from the differential data line in response to the biasing control signal.

BACKGROUND OF THE INVENTION

The present invention relates generally to transferring data, and moreparticularly to a method and apparatus for transferring data on avoltage biased data line.

A computer bus is generally a set of parallel conductors connecting twoor more electrical devices for the purpose of data transfer. One popularbus is the SCSI bus. The SCSI bus is an interface designed for computersand electronic instrumentation to allow communication of data over shortdistances. The SCSI bus is designed to connect independent devices suchas disk drives, tape drives, file servers, video monitors, printers,scanners, and other computers. Several SCSI versions have been developedand standardized, with newer versions being developed to keep pace withchanging computer speeds and requirements. One of the newer standards islow voltage differential (LVD) SCSI, an improved version of differentialSCSI. Differential voltage signals (typically of 400 millivoltsdifference) are used in LVD SCSI, allowing for higher data transferrates and longer distances than the older single-ended SCSI standard. InLVD SCSI, each differential data line of the SCSI bus is comprised oftwo separate bus lines. A binary one is transmitted when the first busline is more positive than the second bus line, and a binary zero istransmitted when the second bus line is more positive than the first busline.

SCSI devices are usually connected from one device to another in a daisychain arrangement. This configuration gives rise to a transmission delayproblem where the ends of the bus, not having the same characteristicimpedance as the bus itself, will reflect a portion of the signal. Thisreflection will cause longer transmission times as the bus attempts toreceive the data signal over the reflected signal. To lessen thisreflection problem, the common practice is to terminate each end of thephysical SCSI bus with a termination circuit or terminator that attemptsto match the characteristic impedance of the SCSI cable. The terminatorsused in LVD SCSI commonly provide a fixed biasing voltage across the twobus lines to keep the receivers from being driven by noise in theabsence of any differential signals.

Unfortunately, due to the fixed biasing voltage the prior art LVDterminators had several drawbacks. One such drawback was that the fixedbiasing voltage swamped out or masked differential data signals at hightransfer rates. The SCSI bus like all transmission lines attenuatessignals as a function of frequency. Accordingly, at high SCSI transferrates, the SCSI bus substantially attenuates the differential datasignals transferred across the SCSI bus. However, the differential datasignals had to overcome the fixed biasing voltage applied by the priorart LVD terminators to the differential data line. If the SCSI busattenuated the differential data signals enough, then the fixed biasingvoltage swamped out or masked the differential data signals to a pointwhere the receivers failed to detect the differential data signals.

Furthermore, the fixed biasing voltage required LVD drivers to drive thedifferential data line with asymmetrical currents in order to generatesymmetrical differential voltages on differential data line. The LVDdrivers had to drive asymmetrical currents because when driving thedifferential data line to a first differential voltage the differentialbiasing voltage hindered in the development of the first differentialvoltage. However, when driving the differential data line to a seconddifferential voltage the differential biasing voltage aided in thedevelopment of the second differential voltage. The main problem withthe asymmetrical current driving requirements was that it generatednoise on the differential data line which limited the transfer rate atwhich data could be transferred reliably.

Therefore, what is needed is a method and apparatus for transferringdata on a voltage biased data line that prevents the biasing voltagefrom swamping out the differential data signals during high speedtransfers and that allows for symmetrical driving of the data line.

SUMMARY OF THE INVENTION

In accordance with one embodiment of the present invention, there isprovided a method of transferring data across a differential data linehaving a first bus line and a second bus line. The method includescomprising the steps of (i) developing a differential biasing voltagebetween the first bus line of the differential data line and the secondbus line of the differential data line, (ii) removing the differentialbiasing voltage from the first bus line and the second bus line, and(iii) transferring data across the differential data line after theremoving step.

Pursuant to another embodiment of the present invention, there isprovided a terminator that provides a differential biasing voltage for adifferential data line having a first bus line and a second bus line.The terminator includes an impedance network and a controllable biasingcircuit. The impedance network is coupled to the first bus line and thesecond bus line and is configured to substantially match acharacteristic impedance of the differential data line. The controllablebiasing circuit includes a control input configured to receive a controlsignal. Furthermore, the controllable biasing circuit is coupled to thedifferential data line and is configured to (i) develop the differentialbiasing voltage between the first bus line and the second bus line, and(ii) remove the differential biasing voltage from the differential dataline based upon the control signal.

Pursuant to yet another embodiment of the present invention, there isprovided a bus interface for controlling a differential bus having adifferential data line that includes a first bus line and a second busline. The bus interface includes a bus controller circuit, a impedancenetwork, and a controllable biasing circuit. The bus controller circuitis coupled to the differential bus and is configured to (i) controltransfer of data across the differential bus, and (ii) generate abiasing control signal prior to data transfer on the differential dataline. The impedance network is coupled to the first bus line and thesecond bus line and is configured to substantially match acharacteristic impedance of the differential data line. The controllablebiasing circuit is coupled to the differential data line and isconfigured to (i) develop a differential biasing voltage between thefirst bus line and the second bus line, and (ii) to remove thedifferential biasing voltage from the differential data line in responseto the biasing control signal.

It is an object of the present invention to provide an improved methodand apparatus for voltage biasing a bus line.

It is also an object of the present invention to provide a new anduseful method and apparatus for voltage biasing a bus line.

It is another object of the present invention to provide a method andapparatus for voltage biasing a bus line with a programmable biasingvoltage.

It is further an object of the present invention to provide an improvedmethod and apparatus for transferring data across a differential dataline.

It is also an object of the present invention to provide a new anduseful method and apparatus for transferring data across a differentialdata line.

It is yet another object of the present invention to provide a methodand apparatus for transferring data across a differential data line thatenables transfer of data with symmetrical currents that drivesymmetrical differential voltages on the differential data line.

It is further an object of the present invention to provide an improvedmethod and apparatus for controlling a bus and terminating at least onebus line of the bus.

It is also an object of the present invention to provide a new anduseful method and apparatus for controlling a bus and terminating atleast one bus line of the bus.

It is yet a further object of the present invention to provide a methodand apparatus for controlling a bus and terminating at least one busline of the bus with an integrated circuit chip in a cost effectivemanner.

The above and other objects, features, and advantages of the presentinvention will become apparent from the following description and theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of a known SCSI bus configuration;

FIG. 2 shows a schematic diagram of a SCSI bus configuration thatincorporates various features of the present invention therein;

FIG. 3 shows a schematic diagram of the biasing control circuit of FIG.2.;

FIG. 4 shows a flowchart of an initialization procedure utilized by theSCSI bus configuration of FIG. 2;

FIG. 5 shows a schematic diagram of the first controllable currentsource of FIG. 2;

FIG. 6 shows a schematic diagram of the second controllable currentsource of FIG. 2; and

FIG. 7 shows a perspective view of an integrated circuit chip whichincorporates the LVD terminator and bus controller of FIG. 2 therein.Note that FIG. 7 shows the substrate 720 located about midway within theintegrated circuit chip 700 between an upper insulating portion ofpackage 710 and a lower insulating portion of package 710.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

While the invention is susceptible to various modifications andalternative forms, a specific embodiment thereof has been shown by wayof example in the drawings and will herein be described in detail. Itshould be understood, however, that there is no intent to limit theinvention to the particular form disclosed, but on the contrary, theintention is to cover all modifications, equivalents, and alternativesfalling within the spirit and scope of the invention as defined by theappended claims.

Referring now to FIG. 1, there is shown a simplified schematic diagramof a known low voltage differential (LVD) SCSI bus configuration 10. Theknown LVD SCSI bus configuration 10 includes a first SCSI device 12, asecond SCSI device 14, and a SCSI bus 20 that couples the first SCSIdevice 12 to the second SCSI device 14. The first SCSI device 12 and thesecond SCSI device 14 may be computer systems, network servers,printers, hard drives, CD-ROM drives, RAID devices, or any otherperipheral device having a LVD SCSI interface. The SCSI bus 20 providesa communications path between the first device 12, the second device 14,and any other SCSI device that may be coupled to the SCSI bus 20. Tothis end, the SCSI bus 20 includes several control lines and data linesthat are utilized for transferring data between devices coupled to theSCSI bus 20. Typically, each data line of the SCSI bus 20 is typicallyterminated and controlled in a similar manner. Therefore, in order tosimplify FIG. 1, only a single differential data line 22 that includes afirst bus line 24 and a second bus line 26 is depicted in FIG. 1. Itshould be noted that the SCSI bus 20 actually has several differentialdata lines that are terminated and controlled in the following describedmanner.

The first device 12 is coupled to a first end of the SCSI bus 20 and asdepicted includes a first terminator 40, a LVD driver 80, and a buscontroller circuit 90. The second device is coupled to a second end ofthe SCSI bus 20 and as depicted includes a second terminator 60, a LVDreceiver 85, and a bus controller circuit 95. It should be noted thateach LVD SCSI device coupled to the SCSI bus 20 has a LVD driver inorder to transmit data and a LVD receiver in order to receive data.However, since only one terminator is coupled to each end of the SCSIbus 20, the SCSI devices that are not coupled to the ends of the SCSIbus need not include a terminator. Furthermore, even the SCSI devices atthe ends of the SCSI bus 20 need not include a terminator since aseparate terminating device may be coupled to the ends of the SCSI bus20.

The first terminator 40 is coupled to a first end of the differentialdata line 22. The first terminator 40 terminates the first end of thedifferential data line 22 in order to reduce signal reflection upon thedifferential data line 22. Furthermore, the first terminator 40impresses a first differential biasing voltage on the first end of thedifferential data line 22. To this end, the first terminator 40 includesa first resistor 42, a first voltage source 44, a second voltage source46, a second resistor 48, a third voltage source 50, a buffer 52, and athird resistor 54. The first resistor 42, the first voltage source 44,the second voltage source 46, and the second resistor 48 arerespectively coupled in series between the first bus line 24 and thesecond bus line 26. Furthermore, the third voltage source 50, the buffer52, and the third resistor 54 are respectively coupled in series betweenground and a node 56 that is between the first voltage source 44 and thesecond voltage source 46.

The first resistor 42 and the second resistor 48 in combination matchthe impedance of the first bus line 24 and the second bus line 26 of thedifferential data line 22. In LVD SCSI, the first bus line 24 and thesecond bus line 26 each typically have a characteristic impedance ofapproximately 110 ohms. Therefore, in order to match the characteristicimpedance of the first and second bus lines 24 and 26, the firstresistor 42 and the second resistor 48 have in combination an impedanceof approximately 110 ohms. Typically, the first resistor 42 and thesecond resistor 48 have substantially equal impedances of about 55 ohmsapiece.

The buffer 52 helps isolate the third voltage source 50 from theremainder of the first terminator 40 and may be implemented as a voltagefollower circuit. In particular, the buffer 52 substantially preventsdifferential current from flowing through the third resistor 54. As aresult of substantially no differential current flowing through thethird resistor 54, the voltage level at the node 56 is substantiallyequal to a third voltage produced by the third voltage source 50. Due tothe node 56 being substantially equal to the third voltage produced bythe third voltage source 50, the third voltage source 50 essentiallysets the center voltage around which differential voltages are appliedto the differential data line 22. For LVD SCSI, a typical third voltageproduced by the third voltage source 50 is approximately 1.25 volts.

Assuming substantially no differential current is flowing through thefirst resistor 42 and the second resistor 48, the first voltage source44 and the second voltage source 46 in combination impress the firstdifferential biasing voltage upon the differential data line 22. Inparticular, the first voltage source 44 impresses a first voltage uponthe first bus line 24 that is greater than the center voltage at node56. Conversely, the second voltage source 46 impresses a second voltageupon the second bus line 26 that is less than the center voltage at node56. The difference between the first voltage on the first bus line 24and the second voltage on the second bus line 26 is the firstdifferential biasing voltage supplied by the first terminator 40. In LVDSCSI, the first voltage source 44 and the second voltage source 46 aretypically each 60 millivolts that in combination impress a firstdifferential biasing voltage upon the differential data line 22 of about120 millivolts.

The bus controller circuit 90 is coupled to the LVD driver 80. The buscontroller circuit 90 is operable to generate control signals whichcause the LVD driver 80 to transmit data across the differential dataline 22. Furthermore, the bus controller circuit 90 is further operableto generate SCSI protocol control signals for transmission across thecontrol lines of the SCSI bus 20 and to receive SCSI protocol controlsignals from the control lines of the SCSI bus 20. The bus controllercircuit 90 is also operable to control an interface between the SCSI bus20 and the first device 12. For example, if the first device 12 is acomputer system, then the bus controller circuit 90 is operable tocontrol transfer of data between the SCSI bus 20 and the computer systemin which the bus controller circuit 90 resides. Likewise, if the firstdevice 12 is a hard drive, then the bus controller circuit 90 isconfigured to control transfer of data between the SCSI bus cable 20 andthe hard drive in which the bus controller circuit 90 resides. It shouldbe noted that the bus controller circuit 90 may be further operable toprocess output signals from a LVD receiver (not shown) of the firstdevice 12.

The LVD driver 80 drives the differential data line 22 of the SCSI bus20 in order to transfer data across the differential data line 22. Inparticular, the LVD driver 80 (i) drives the differential data line 22to a first differential voltage in order to transfer a binary one acrossthe differential data line 22, (ii) drives the differential data line 22to a second differential voltage in order to transfer a binary zeroacross the differential data line 22, and (iii) allows the first voltagesources 44 and 64 and the second voltage sources 46 and 66 of the firstand second terminators 40 and 60 to drive the differential data line 22to their respective differential biasing voltages in order to transferno data across the differential data line 22. Furthermore, the LVDdriver 80 is implemented to draw substantially no current from thedifferential data line 22 during periods when the LVD driver 80 is notdriving the differential data line 22. To this end, the LVD driver 80includes a first current driver 82 that is coupled to the first bus line24 of the differential data line 22 and a second current driver 84 thatis coupled to the second bus line 26 of the differential data line 22.The first current driver 82 and the second current driver 84 in responseto control signals received from the bus controller circuit 90 generateand source currents upon said differential data line 22 that causeappropriate differential voltages to be impressed upon the differentialdata line 22.

The second terminator 60 is coupled to a second end of the differentialdata line 22. The second terminator 60 terminates the second end of thedifferential data line 22 in order to reduce signal reflection upon thedifferential data line 22. Furthermore, the second terminator 60impresses a second differential biasing voltage on the second end of thedifferential data line 22. To this end, the second terminator 60includes a first resistor 62, a first voltage source 64, a secondvoltage source 66, a second resistor 68, a third voltage source 70, abuffer 72, and a third resistor 74. The first resistor 62, the firstvoltage source 64, the second voltage source 66, and the second resistor68 are respectively coupled in series between the first bus line 24 andthe second bus line 26. Furthermore, the third voltage source 70, thebuffer 72, and the third resistor 74 are respectively coupled in seriesbetween ground and a node 76 that is between the first voltage source 64and the second voltage source 66.

The first resistor 62 and the second resistor 68 in combination matchthe impedance of the first bus line 24 and the second bus line 26 of thedifferential data line 22. In LVD SCSI, the first bus line 24 and thesecond bus line 26 each typically have a characteristic impedance ofapproximately 110 ohms. Therefore, in order to match the characteristicimpedance of the first and second bus lines 24 and 26, the firstresistor 62 and the second resistor 68 have in combination an impedanceof approximately 110 ohms. Typically, the first resistor 62 and thesecond resistor 68 have substantially equal impedances of about 55 ohmsapiece.

The buffer 72 helps isolate the third voltage source 70 from theremainder of the second terminator 60 and may be implemented as avoltage follower circuit. In particular, the buffer 72 substantiallyprevents differential current from flowing through the third resistor74. As a result of substantially no differential current flowing throughthe third resistor 74, the voltage level at the node 76 is substantiallyequal to a third voltage produced by the third voltage source 70. Due tothe node 76 being substantially equal to the third voltage produced bythe third voltage source 70, the third voltage source 70 essentiallysets the center voltage around which differential voltages are appliedto the differential data line 22. For LVD SCSI, a typical third voltageproduced by the third voltage source 50 is approximately 1.25 volts.

Assuming substantially no differential current is flowing through thefirst resistor 62 and the second resistor 68, the first voltage source64 and the second voltage source 66 in combination impress the firstdifferential biasing voltage upon the differential data line 22. Inparticular, the first voltage source 64 impresses a first voltage uponthe first bus line 24 that is greater than the center voltage at node76. Conversely, the second voltage source 66 impresses a second voltageupon the second bus line 26 that is less than the center voltage at node76. The difference between the first voltage on the first bus line 24and the second voltage on the second bus line 26 is the seconddifferential biasing voltage supplied by the second terminator 60. InLVD SCSI, the first voltage source 64 and the second voltage source 66are typically each 60 millivolts that in combination impress a seconddifferential biasing voltage upon the differential data line 22 of about120 millivolts.

The bus controller circuit 95 is coupled to the LVD receiver 85. The buscontroller circuit 95 is operable to process output signals receivedfrom the LVD receiver 85. Furthermore, the bus controller circuit 95 isfurther operable to generate SCSI protocol control signals fortransmission across the control lines of the SCSI bus 20 and to receiveSCSI protocol control signals from the control lines of the SCSI bus 20.The bus controller circuit 95 is also operable to control an interfacebetween the SCSI bus 20 and the second device 14. For example, if thesecond device 14 is a computer system, then the bus controller circuit95 is operable to control transfer of data between the SCSI bus 20 andthe computer system in which the bus controller circuit 95 resides.Likewise, if the second device 14 is a hard drive, then the buscontroller circuit 95 is configured to control transfer of data betweenthe SCSI bus 20 and the hard drive in which the bus controller circuit95 resides. It should be noted that the bus controller circuit 95 may befurther operable to generate control signals which cause an LVD driver(not shown) of the second device 14 to transmit data across thedifferential data line 22.

The LVD receiver 85 is coupled to the differential data line 22 of theSCSI bus 20. In general, the LVD receiver 85 is operable to generate anoutput signal that is representative of a differential voltage impressedon the differential data line 22. To this end, the LVD receiver 85 maybe implemented as a differential amplifier 87 that includes a firstinput that is coupled to the first bus line 24 and a second input thatis coupled to the second bus line 26. The differential amplifier 87 isthen operable to generate an output signal that is representative of thevoltage difference between the first bus line 24 and the second bus line26. In particular, the differential amplifier 97 is operable to (i)generate an output signal having a low voltage (e.g. a V_(SS) of 0volts) when a -400 millivolt difference exists between the first busline 24 and the second bus line 26, and (ii) a high voltage (e.g. aV_(DD) of 3.3 volts) when a +400 millivolt difference exists between thefirst bus line 24 and the second bus line 26. Furthermore, the LVDreceiver 85 draws substantially no current from the differential dataline 22.

In operation, each differential data line of the SCSI bus 20 has threestates: (1) an idle or quiescent state, (2) an asserted state, and (3) anegated state. In order to simplify the following discussion, it will beassumed that the components of the first and second terminators 40 and60 are substantially matched. In particular, it will be assumed that (i)the first and second resistors 42, 48, 62, and 68 are each equal to 55ohms; (ii) the first and second voltage sources 44, 46, 54 and 64 areeach equal to 60 millivolts; (iii) the third voltage sources 50 and 70are each equal to 1.25 volts; and (iv) the third resistors 54 and 74 areeach equal to 150 ohms.

During the idle state, no SCSI device drives the differential data line22. In particular, the bus controller circuit 90 via a control signalcauses the LVD driver 80 to drive no current on the differential dataline 22. Furthermore, since the LVD receiver 85 draws substantially nocurrent, any current generated through the differential data line 22would be due to the first and second terminators 40 and 60. However,since the first terminator 40 and the second terminator 60 havesubstantially matched components, the first terminator 40 and the secondterminator 60 will both impress substantially equal voltages upon thefirst bus line 24 and the second bus line 26 during the idle state. As aresult, substantially no current flows through the first bus line 24 andthe second bus line 26. Furthermore, as stated above, substantially nodifferential current flows through the third resistors 54 and 74.According, substantially no current flows in the SCSI bus configuration10 and the third voltage sources 50 and 70 will respectively impress acenter voltage of 1.25 volts on the nodes 56 and 76. The first voltagesources 44 and 64 will each then raise the center voltage at nodes 56and 76 and impress 1.31 volts (1.25 volts+60 millivolts) on the ends ofthe first bus line 24. Conversely, the second voltage sources 46 and 66will lower the center voltage at nodes 56 and 76 and impress 1.19 volts(1.25 volts-60 millivolts) on the ends of the second bus line 26. As aresult of the above, a differential biasing voltage of 120 millivolts(1.31 volts-1.19 volts) is impressed upon the differential data line 22.In response to the 120 millivolt differential biasing voltage, the LVDreceiver 85 generates an output signal that is representative of the 120millivolt differential biasing voltage. The bus controller circuit 95then determines from this output signal that no data is beingtransferred.

During the asserted state, the LVD driver 80 causes a first differentialvoltage to be impressed on the differential data line 22. To this end,the bus controller circuit 90 via a control signal causes the LVD driver80 to sink a 9 milliamp current from the first bus line 24 and to sourcea 9 milliamp current on the second bus line 26. Furthermore, since theLVD receiver 85 draws substantially no current from the differentialdata line 22, the current produced by the LVD driver 80 flows solelythrough the first and second terminators 40 and 60. Moreover, since thefirst terminator 40 and the second terminator 60 have substantiallymatched components, the first terminator 40 and the second terminator 60will have substantially matched impedances, thus causing half of thesourced current (4.5 milliamps) to flow from the LVD driver 80 to thefirst terminator 40 and half of the sourced current (4.5 milliamps) toflow from the LVD driver 80 through the second terminator 60. Likewise,half of the sinked current (4.5 milliamps) flows from the firstterminator 40 to the LVD driver 80 and half of the sinked current (4.5milliamps) flows from the second terminator 60 to the LVD driver 80.

As stated above, substantially no differential current flows through thethird resistors 54 and 74. According, the third voltage sources 50 and70 respectively impress a center voltage of 1.25 volts on the nodes 56and 76, and the LVD driver 80 causes a 4.5 milliamp current to flowthrough each of the first and a second resistors 42, 48, 62, and 68. Thefirst voltage sources 44 and 64 each raise the center voltage at nodes56 and 76; however, since the 4.5 milliamp current is flowing from thesecond bus line 26 to the first bus line 24, the voltages generated bythe first resistors 42 and 62 have polarities that are opposite of thepolarities of the first voltage sources 44 and 64. Accordingly, thefirst voltage sources 44 and 64 hinder the LVD driver 80 in impressingthe first differential voltage on the differential data line 22. Inparticular, the voltage generated across the first resistors 42 and 62lower the center voltage by 247.5 millivolts (4.5 milliamps×55 ohms)while the first voltage sources counteract the effect by 60 millivolts,thus resulting in a first voltage of 1.0625 (1.25 volts-247.5millivolts+60 millivolts) being impressed on the first bus line 24.Conversely, the voltage generated across the second resistors 48 and 68raise the center voltage by 247.5 millivolts (4.5 milliamps×55 ohms)while the second voltage sources 46 and 66 counteract the effect by 60millivolts, thus resulting in a second voltage of 1.4375 volts (1.25volts+247.5 millivolts-60 millivolts) being impressed on the second busline 26. As a result of the above, a first differential voltage of -375millivolts (1.0625 volts-1.4375 volts) is impressed upon thedifferential data line 22. In response to the -375 millivoltdifferential voltage, the LVD receiver 85 generates an output signalthat is representative of the -375 millivolt differential voltage. Thebus controller circuit 95 then determines from this output signal that abinary one is being transferred on the differential data line 22.

During the negated state, the LVD driver 80 causes a second differentialvoltage to be impressed on the differential data line 22. To this end,the bus controller circuit 90 via a control signal causes the LVD driver80 to source a 4.5 milliamp current on the first bus line 24 and to sinka 4.5 milliamp current from the second bus line 26. Furthermore, sincethe LVD receiver 85 draws substantially no current from the differentialdata line 22, the current produced by the LVD driver 80 flows solelythrough the first and second terminators 40 and 60. Moreover, since thefirst terminator 40 and the second terminator 60 have substantiallymatched components, the first terminator 40 and the second terminator 60have substantially matched impedances, thus causing half of the sourcedcurrent (2.25 milliamps) to flow from the LVD driver 80 to the firstterminator 40 and half of the sourced current (2.25 milliamps) to flowfrom the LVD driver 80 to the second terminator 60. Likewise, half ofthe sinked current (2.25 milliamps) flows from the first terminator 40to the LVD driver 80 and half of the sinked current (2.25 milliamps)flows from the second terminator 60 to the LVD driver 80.

As stated above, substantially no differential current flows through thethird resistors 54 and 74. According, the third voltage sources 50 and70 respectively impress a center voltage of 1.25 volts on the nodes 56and 76, and the LVD driver 80 causes a 2.25 milliamp current to flowthrough each of the first and the second resistors 42, 48, 62, and 68.The first voltage sources 44 and 64 each raise the center voltage atnodes 56 and 76. Furthermore, since the 2.25 milliamp current flows fromthe first bus line 24 to the second bus line 26, the voltages generatedacross the first resistors 42 and 62 have polarities that are equal tothe polarities of the first voltage sources 44 and 64. Accordingly, thefirst voltage sources 44 and 64 aid the LVD driver 80 in impressing thesecond differential voltage on the differential data line 22. Inparticular, the voltage generated across the first resistors 42 and 62will raise the center voltage by 123.75 millivolts (2.25 milliamps×55ohms), and the first voltage sources will aid the effect by 60millivolts, thus resulting in a first voltage of 1.43375 volts (1.25volts+123.75 millivolts+60 millivolts) impressed on the first bus line24. Conversely, the voltage generated across the second resistors 48 and68 lowers the center voltage by 123.75 millivolts (2.25 milliamps×55ohms), and the second voltage sources 46 and 66 aid the effect by 60millivolts, thus resulting in a second voltage of 1.06625 volts (1.25volts-123.75 millivolts-60 millivolts) being impressed on the second busline 26. As a result of the above, a second differential voltage of367.5 millivolts (1.43375 volts-1.06625 volts) is impressed upon thedifferential data line 22. In response to the 367.5 millivoltdifferential voltage, the LVD receiver 85 generates an output signalthat is representative of the 367.5 millivolt differential voltage. Thebus controller circuit 95 then determines from this output signal that abinary zero is being transferred on the differential data line 22.

The above known LVD SCSI bus configuration 10 has several drawbacks. Themain drawbacks are due to the fixed differential biasing voltagesupplied by the first and second voltage sources 44, 46, 64, and 66. Ascan be seen from the above description, the known LVD driver 80 wasrequired to supply asymmetrical currents to the differential data line22 in order to generate the substantially symmetrical differentialvoltages of the asserted and negated states. What is meant herein byasymmetric currents is two currents that have substantially differentmagnitudes and opposite polarities. For example, the above LVD driver 80applied a first current of -9.0 milliamps to the first bus line 24during the asserted state but applied a second current of +4.5 milliampsto the first bus line 24 during the negated state. The first current andthe second current had substantially different magnitudes (9.0 and 4.5milliamps respectively) and opposite polarities (negative and positivepolarity respectively). What is meant herein by symmetrical differentialvoltages are two differential voltages that have substantially equalmagnitudes and opposite polarities. For example, the above LVD driver 80caused a first differential voltage of -375 millivolts to be impressedon the differential data line 22 during the asserted state, and caused asecond differential voltage of +367.5 millivolts to be impressed on thedifferential data line 22 during the negated state. The firstdifferential voltage and the second differential voltage hadsubstantially equal magnitudes (375 and 367.5 millivolts respectively)and opposite polarities (negative and positive polarities respectively).The asymmetrical current required of the above LVD driver 80 generatedadditional noise on the differential data line 22. This additional noiseprevented reliable transfer of data at rates above 100 Megabytes/second.

In order to provide meaning to the terms "substantially equalmagnitudes" and "substantially different magnitudes," it should beappreciated that if a first magnitude is more than 20 percent differentthan a second magnitude then the first magnitude is substantiallydifferent than the second magnitude. For example, if X/Y=2.0000, then Xand Y have substantially different magnitudes. Moreover, if a firstmagnitude is less than 20 percent different than a second magnitude thenthe first magnitude is substantially equal to the second magnitude. Forexample, if X/Y=1.0204, then X and Y have substantially equalmagnitudes.

A further drawback of the known LVD SCSI configuration 10 is that thefixed differential biasing voltage supplied by the first and secondvoltage sources 44, 46, 64, and 66 swamped out or masked differentialdata signals on the differential data line 22. As can be seen from theabove discussion, the first differential voltage generated during theasserted state must overcome the differential biasing voltage generatedby the first and second voltage sources 44, 46, 64, and 66. However, dueto cable attenuation especially at high frequencies such as 100 MHz, thefirst differential signal may fail to sufficiently overcome thedifferential biasing voltage. As a result, the LVD receiver 85 may failto receive the transmitted binary one associated with the assertedstate. Likewise, due to the cable attenuation, the second differentialvoltage generated during the negated state may fail to add sufficientlyto the differential biasing voltage. As a result, the LVD receiver 85may fail to receive the transmitted binary zero associated with thenegated state.

Yet another drawback of the known LVD SCSI configuration 10 is that thefirst and second terminators 40 and 60 must be highly matched in orderto impress substantially equal differential biasing voltages to each endof the differential data line 22. If the differential biasing voltageapplied to each end of the differential data line by the firstterminator 40 and the second terminator 60 were not substantiallymatched, then loop current flowed through the differential data line 22.The loop current if large enough could cause changes to the differentialvoltages on the differential data line 22 which may be misinterpreted asdata by the LVD receiver 85. In order to reduce loop currents, costlymanufacturing processes were used to match the components of the firstand second terminators 40 and 60. For example, it was common practice toutilize thin film resistors for the first and second resistors 42, 48,62, and 68 and to individually laser trim each resistor in order tomatch the resistors. It should be appreciated that this process waslabor intensive and very costly.

As a result, there is a need for a LVD SCSI bus configuration thatallows the LVD driver to generate symmetrical currents to producesymmetrical differential voltages in order to reduce noise on thedifferential data line. There is also a need for a LVD SCSI busconfiguration that does not swamp out the differential data signals athigh transfer rates. Furthermore, there is a need for a LVD SCSI busconfiguration that reduces loop currents without requiring costlymanufacturing processes.

Shown in FIG. 2 is a LVD SCSI bus configuration 110 which incorporatestherein features of the present invention which address the above needs.The LVD SCSI bus configuration 110 includes a LVD terminator 115, a SCSIbus 120, a LVD driver 180, and a bus controller circuit 190. The SCSIbus 120 includes several control lines and data lines that are utilizedfor transferring data between devices coupled to the SCSI bus 120. Inorder to simplify FIG. 2, only a single differential data line 122 thatincludes a first bus line 124 and a second bus line 126 is depicted inFIG. 2. It should be noted that the SCSI bus 120 actually has severaldifferential data lines that are terminated and controlled in thefollowing described manner.

The LVD terminator 115 terminates a first end of the differential dataline 122 and impresses a differential biasing voltage upon the first endof the differential data line 122. To this end, the LVD terminator 115includes an impedance network 130, a controllable biasing circuit 140,and a biasing control circuit 160. The impedance network 130 is coupledto the first end of the differential data line 122. The impedancenetwork 130 terminates the first end of the differential data line 122in order to reduce signal reflection upon the differential data line122. To this end, the impedance network 130 includes a first resistor132, a second resistor 134, and a third resistor 136. The first resistor132, and the second resistor 134 are coupled in series between the firstbus line 124 and the second bus line 126. Furthermore, the thirdresistor 136 having an impedance of approximately 150 ohms is coupledbetween the controllable biasing circuit 140 and a node 138 that isbetween the first resistor 132 and the second resistor 134. The firstresistor 132 and the second resistor 134 in combination match theimpedance of the first bus line 124 and the second bus line 126 of thedifferential data line 122. In LVD SCSI, the first bus line 124 and thesecond bus line 126 each typically have a characteristic impedance ofapproximately 110 ohms. Therefore, in order to match the characteristicimpedance of the first and second bus lines 124 and 126, the firstresistor 132 and the second resistor 134 each have an impedance of about55 ohms which in combination provide an impedance of approximately 110ohms to the differential data line 122.

The controllable biasing circuit 140 is coupled between the impedancenetwork 130 and the biasing control circuit 160. The controllablebiasing circuit 140 impresses a differential biasing voltage on thefirst end of the differential data line 122. In particular, thecontrollable biasing circuit 140 impresses a differential biasingvoltage having a differential voltage level that is based upon controlsignals received from the biasing control circuit 160. To this end, thecontrollable biasing circuit 140 includes a first controllable currentsource 142, a second controllable current source 144, a first voltagesource 146, and a buffer 148. The first controllable current source 142is coupled to the first bus line 124. The first controllable currentsource is operable to produce a first current that has a first currentlevel that is based on a first biasing control signal received from thebiasing control circuit 160. Likewise, the second controllable currentsource 144 is coupled to the second bus line 126 and is operable toproduce a second current that has a second current level that is basedon a second biasing control signal received from the biasing controlcircuit 160. The first and second current sources 142 and 144 incombination cause a current to flow through the first and secondresistor 132 and 134 that is based on the first and second biasingcontrol signals received from the biasing control circuit 160. Thecurrent through the first and second resistors 132 and 134 generates adifferential biasing voltage that is impressed upon the differentialdata line 122.

Moreover, the buffer 148 couples the first voltage source 146 to thethird resistor 136 of the impedance network 130. The buffer 148 helpsisolate the first voltage source 146 from the impedance network 130 andmay be implemented as a voltage follower circuit. In particular, thebuffer 148 substantially prevents differential current from flowingthrough the third resistor 136. As a result of substantially nodifferential current flowing through the third resistor 136, the voltagelevel at the node 138 is substantially equal to a first voltage producedby the first voltage source 146. Due to the node 138 being substantiallyequal to the first voltage produced by the first voltage source 146, thefirst voltage source 146 essentially sets the center voltage aroundwhich differential voltages are applied to the differential data line122. In a preferred embodiment, the first voltage source 146 produces afirst voltage of approximately 1.25 volts.

The biasing control circuit 160 is coupled to the first controllablecurrent source 142, the second controllable current source 144, thefirst bus line 124, the second bus line 126, and the bus controllercircuit 190. In general, the biasing control circuit 160 is operable tocontrol the first controllable current source 142, and the secondcontrollable current source 144. To this end, as shown in FIG. 3, thebiasing control circuit 160 includes a selector 162, biasing controllogic 164, a first reference voltage source 166, a second referencevoltage source 168, and a window comparator 170. The selector 162 iscoupled to the first bus line 124, the second bus line 126, the biasingcontrol logic 164, and the window comparator 170. As stated above, theSCSI bus 120 includes several differential data lines. The selector 162is coupled to each of these differential data lines. The selector 162includes several switches that in response to a selection signalreceived from the biasing control logic 164 enable the selector 162 toselectively couple the bus lines of a single differential data line tothe window comparator 170. While the biasing control circuit 160 couldbe implemented to have a separate window comparator 170 for eachdifferential data line 122, the use of the selector 162 with the singlewindow comparator 170 greatly reduces the cost of the biasing controlcircuit 160. This is especially true in wide LVD SCSI where the SCSI bushas 16 differential data lines and 2 differential parity lines thatwould each require a separate window comparator.

The first reference voltage source 166 is coupled to the windowcomparator 170 and is operable to generate a first reference voltage.Similarly, the second reference voltage source 168 is coupled to thewindow comparator 170 and is operable to generate a second referencevoltage. The first reference voltage produced by the first referencevoltage source 166 is substantially equal to a first desired voltage forthe first bus line 124 during the idle state. Similarly, the secondreference voltage produced by the second reference voltage source 168 issubstantially equal to second desired voltage for the second bus line126 during the idle state. In a preferred embodiment, the first andsecond reference voltage sources 166 and 168 are implemented with knownband gap circuitry. Furthermore, the first reference voltage source 166is implemented to generate 1.31 volts for the first reference voltage,and the second reference voltage source 168 is implemented to generate1.19 volts for the second reference voltage.

The window comparator 170 is coupled to the selector 162, the firstreference voltage source 166, and the second reference voltage source168. In order to simplify the following discussion, it is assumed thatthe selector 162 has coupled the first bus line 124 and the second busline 126 to the window comparator 170. The window comparator 170 isoperable to compare a first voltage of the first bus line 124 to thefirst reference voltage and to generate a first status signal that isindicative of whether the first voltage satisfies a predeterminedrelationship to the first reference voltage. The window comparator 170is also operable to compare a second voltage of the second bus line 126to the second reference voltage and to generate a second status signalthat is indicative of whether the second voltage satisfies apredetermined relationship to the second reference voltage.

To this end, the window comparator 170 includes a first comparator 172and a second comparator 174. A first input of the first comparator 172is coupled to the first reference voltage source 166 and a second inputof the first comparator 172 is coupled to the first bus line 124 via theselector 162. Similarly, a first input of the second comparator 174 iscoupled to the second reference voltage source 168 and a second input ofthe second comparator 174 is coupled to the second bus line 126 via theselector 162. The first comparator 172 is configured to (i) generate ahigh output (e.g. a V_(DD) of 3.3 volts) for the first status signal ifthe first voltage of the first bus line 124 is less than the firstreference voltage of the first reference voltage source 166, and (ii)generate a low output (e.g. a V_(SS) of 0 volts) for the first statussignal if the first voltage of the first bus line 124 is not less thanthe first reference voltage of the first reference voltage source 166.Conversely, the second comparator 174 is configured to (i) generate ahigh voltage (e.g. a V_(DD) of 3.3 volts) for the second status signalif the second voltage of the second bus line 126 is greater than thesecond reference voltage of the second reference voltage source 168, and(ii) generate a low voltage (e.g. 0 volts) for the second status signalif the second voltage of the second bus line 126 is not greater than thesecond reference voltage of the second reference voltage source 168. Inthe preferred embodiment, the first and second comparator 172 and 174are each implemented in a known manner with differential amplifiercircuitry.

The biasing control logic 164 is coupled to the first controllablecurrent source 142, the second controllable current source 144, thewindow comparator 170, and the bus controller circuit 180. The biasingcontrol logic 164 is generally configured to (i) receive signals fromthe window comparator 170 and the bus controller circuit 180, and (ii)generate from the received signals, appropriate first and second biasingcontrol signals for the first the second controllable current source 142and 144, respectively.

Referring back to FIG. 2, the LVD driver 180 drives the differentialdata line 122 of the SCSI bus 120 in order to transfer data across thedifferential data line 122. In particular, the LVD driver 180 (i) drivesthe differential data line 122 to a first differential voltage in orderto transfer a binary one across the differential data line 122, (ii)drives the differential data line 122 to a second differential voltagein order to transfer a binary zero across the differential data line122, and (iii) allows the controllable biasing circuit 140 to drive thedifferential data line 122 to the proper differential biasing voltage inorder to transfer no data across the differential data line 122.Furthermore, the LVD driver 180 draws substantially no current from thedifferential data line 122 during period when the LVD driver 180 is notdriving the differential data line 122. To this end, the LVD driver 180includes a first current driver 182 that is coupled to the first busline 124 of the differential data line 122 and a second current driver184 that is coupled to the second bus line 126 of the differential dataline 122. The first current driver 182 and the second current driver 184in response to control signals received from the bus controller circuit190 generate and source currents upon said differential data line 122that cause appropriate differential voltages to be impressed upon thedifferential data line 122.

The bus controller circuit 190 is coupled to the LVD driver 180. The buscontroller circuit 190 is operable to generate control signals whichcause the LVD driver 180 to transmit data across the differential dataline 122. Furthermore, the bus controller circuit 190 is furtheroperable to generate SCSI protocol control signals for transmissionacross the control lines of the SCSI bus 120 and to receive SCSIprotocol control signals from the control lines of the SCSI bus 120. Thebus controller circuit 190 is also operable to control an interfacebetween the SCSI bus 120 and the device in which the bus controllercircuit 190 resides. For example, if bus controller circuit 190 iswithin a computer system, then the bus controller circuit 190 isoperable to control transfer of data between the SCSI bus 120 and thecomputer system. Likewise, if bus controller circuit 190 is within ahard drive, then the bus controller circuit 190 is configured to controltransfer of data between the SCSI bus 120 and the hard drive.Furthermore, the bus controller circuit 190 is further operable todetermine that data transfer is about to begin on the differential dataline 122 and to transmit to the biasing control circuit 160 a controlsignal that indicates data transfer is to begin on the differential dataline 122. It should be noted that the bus controller circuit 190 may befurther operable to process output signals from a LVD receiver (notshown).

It should be noted that each end of the SCSI bus 120 needs to beterminated in order for proper operation. Furthermore, it should also benoted that since both ends of the SCSI bus 120 in the preferredembodiment are terminated in a similar manner only one end of the SCSIbus 120 is illustrated in FIG. 2.

Prior to operation of the SCSI bus 120, the SCSI bus configuration 110goes through an initialization procedure 400 which is depicted in FIG.4. The initialization procedure 400 essentially programs the first andsecond controllable current sources 142 and 144. The initializationprocedure 400 begins in step 402 with the bus controller circuitgenerating a first control signal that causes the LVD driver 190 not todrive the differential data line 122. The biasing control circuit 160then in step 404 generates a selection signal that causes the selector162 to couple the first bus line 124 and the second bus line 126 to thewindow comparator 170. Then in step 406, the biasing control circuit 160generates a first biasing control signal and a second biasing controlsignal. In particular, the biasing circuit 160 generates the firstbiasing control signal to cause the first controllable current source144 to produce a first current that is less than the current required togenerate the appropriate differential biasing voltage. Likewise, thebiasing circuit 160 generates the second biasing control signal to causethe second controllable current source 144 to produce a second currentthat is less than the current required to generate the appropriatedifferential biasing voltage. The first current and second current flowthrough the first and second resistors 132 and 134 thus causing a firstvoltage to be impressed upon the first bus line 124 and a second voltageto be impressed upon the second bus line 126. It should be noted thatsubstantially no differential current flows through the third resistor150 due to the buffer 148. As a result, the first voltage source 146substantial impresses its 1.25 volt voltage upon the node 138, thuscreating a center voltage around which differential voltages areimpressed upon the differential data line 122.

The window comparator 170 in step 408 generates a first and a secondstatus signal. The first status signal indicates whether the firstvoltage on the first bus line has a predetermined relationship to thefirst reference voltage of the first reference voltage source 166, andthe second status signal indicates whether the second voltage on thesecond bus line 126 has a predetermined relationship to the secondreference voltage of the second reference voltage source 168. Inparticular, the window comparator 170 generates (i) a high output (e.g.a V_(DD) of 3.3 volts) for the first status signal if the first voltageon the first bus line 124 is less than a first reference voltage of 1.31volts, and (ii) a low output (e.g. a V_(SS) of 0 volts) for the firststatus signal if the first voltage on the first bus line 124 is not lessthan the first reference voltage of 1.31 volts. Furthermore, the windowcomparator 170 generates (i) a high voltage signal (e.g. a V_(DD) of 3.3volts) for the second status signal if the second voltage on the secondbus line 126 is greater than the second reference voltage of 1.19 volts,and (ii) a low voltage signal (e.g. a V_(SS) of 0 volts) for the firststatus signal if the first voltage on the second bus line 126 is notgreater than the second reference voltage of 1.19 volts.

The biasing control logic 164 then adjusts the currents generated by thefirst and second controllable current sources 142 and 144 dependent uponthe first and second status signals. In particular, the biasing controllogic 164 in step 412 causes the first controllable current source 142to increase its current if the first status signal has a high voltagelevel. To this end, the biasing control logic 164 generates a new firstbiasing control signal that will cause the first controllable currentsource 142 to increase the magnitude of its current. Likewise, thebiasing control logic in step 414 causes the second controllable currentsource 144 to increase its current if the first status signal has a highvoltage level. To this end, the biasing control logic 164 generates anew second biasing control signal that will cause the secondcontrollable current source 144 to increase the magnitude of itscurrent. Increasing the magnitude of the first current produced by thefirst controllable current source 142 increases the magnitude of thefirst voltage on the first bus line 124. Similarly, increasing themagnitude of the second current produced by the second controllablecurrent source 144 increases the magnitude of the second voltage on thesecond bus line 126.

The procedure then returns to step 408 in order for the windowcomparator 170 to determine whether the first voltage on the first busline 124 and the second voltage on the second bus line 126 need to befurther adjusted.

The procedure 400 continues to adjust the first and second currents ofthe first and second controllable current sources 142 and 144 until adifferential voltage substantially equal to 120 millivolts (1.31volts-1.19 volts) centered around 1.25 volts is developed between thefirst bus line and the second bus line. It should be noted that theinitialization procedure 400 in the preferred embodiment is applied toeach of the differential data lines of the SCSI bus 120. Furthermore, itshould be noted that while the initialization procedure 400 may beutilized each time the differential biasing voltage needs to bedeveloped between the first and second bus lines 124 and 126, in thepreferred embodiment the first and second controllable current sources142 and 144 are programmed to generate the appropriate first and secondcurrents in response to biasing control signals from the biasing controlcircuit 160.

Like the prior art SCSI bus configuration 10 of FIG. 1, eachdifferential data line of the SCSI bus 120 may be in one of three statesduring operation: (1) an idle or quiescent state, (2) an asserted state,and (3) a negated state. During the idle state, no SCSI device drivesthe differential data line 122 and the controllable bias circuit 140impresses a differential biasing voltage upon the differential data line122. To this end, the bus controller 190 via a control signal causes theLVD driver 180 to drive no current on the differential data line 122 andthe biasing control circuit 160 generates first and second biasingcontrol signals that cause the first and second controllable currentsources 142 and 144 to generate currents through the first and thesecond resistors 132 and 134. In particular, the biasing control circuit160 generates a first biasing control signal and a second biasingcontrol signal that cause the first and second controllable currentsources 142 and 144 to generate currents having magnitudes equal tothose obtained from the initialization procedure 400. As a result, thefirst and second controllable current sources 142 and 144 generatecurrent through the first and second resistors 132 and 134 that cause adifferential biasing voltage of 120 millivolts to be impressed upon thedifferential data line 122.

During the asserted state, the LVD driver 180 causes a firstdifferential voltage to be impressed on the differential data line 122.To this end, the biasing control circuit 160 in response to a signalreceived from the bus controller 190 generates first and second biasingcontrol signals that cause the first and second controllable currentsources 142 and 144 to generate substantially no current. Furthermore,the bus controller circuit 90 via a control signal causes the LVD driver190 to sink a 7.2 milliamp current from the first bus line 124 and tosource a 7.2 milliamp current on the second bus line 126. It should benoted that without laser trimming, thin film resistors may be costeffectively manufactured having impedances maintained within ±15% of thedesired impedance level. Accordingly, a second terminator (not shown)coupled to the other end (not shown) of the SCSI bus 120 will have acharacteristic impedance relatively close to the characteristicimpedance of the first terminator 115. Therefore, substantially half ofthe sourced current (3.6 milliamps) flows from the LVD driver 180 to thefirst terminator 115 and half of the sourced current (3.6 milliamps)flows from the LVD driver 180 to the second terminator. Likewise, halfof the sinked current (3.6 milliamps) flows from the first terminator115 to the LVD driver 180 and half of the sinked current (3.6 milliamps)flows from the second terminator to the LVD driver 180.

As stated above, substantially no differential current flows through thethird resistor 136. Accordingly, the first voltage source 146respectively impresses a center voltage of 1.25 volts on the node 138,and the LVD driver 180 causes a 3.6 milliamp current to flow througheach of the first and the second resistors 132 and 134. Since a 3.6milliamp current is flowing from the second bus line 126 to the firstbus line 124, the voltage generated across the first resistor 132 lowersthe center voltage by 198 millivolts (3.6 milliamps×55 ohms), thusresulting in a first voltage of 1.052 (1.25 volts-198 millivolts) beingimpressed on the first bus line 124. Conversely, the voltage generatedacross the second resistor 134 raise the center voltage by 198millivolts (3.6 milliamps×55 ohms), thus resulting in a second voltageof 1.448 volts (1.25 volts+198 millivolts) being impressed on the secondbus line 126. As a result of the above, a first differential voltage of-396 millivolts (1.052 volts-1.448 volts) is impressed upon thedifferential data line 122. In response to the -396 millivoltdifferential voltage, a LVD receiver (not shown) generates an outputsignal that is representative of the -396 millivolt differentialvoltage. A bus controller circuit then determines from this outputsignal that a binary one is being transferred on the differential dataline 122.

During the negated state, the LVD driver 180 causes a seconddifferential voltage to be impressed on the differential data line 122.To this end, the biasing control circuit 160 in response to a signalreceived from the bus controller 190 generates first and second biasingcontrol signals that cause the first and second controllable currentsources 142 and 144 to generate substantially no current. Furthermore,the bus controller 190 via a control signal causes the LVD driver 190 tosource a 7.2 milliamp current on the first bus line 124 and to sink a7.2 milliamp current from the second bus line 126. It should be notedthat without laser trimming, thin film resistors may be cost effectivelymanufactured having impedances maintained within ±15% of the desiredimpedance level. Accordingly, a second terminator (not shown) coupled tothe other end (not shown) of the SCSI bus 120 will have a characteristicimpedance relatively close to the characteristic impedance of the firstterminator 115. Therefore, substantially half of the sourced current(3.6 milliamps) flows from the LVD driver 180 to the first terminator115 and half of the sourced current (3.6 milliamps) flows from the LVDdriver 180 to the second terminator. Likewise, half of the sinkedcurrent (3.6 milliamps) flows from the first terminator 115 to the LVDdriver 180 and half of the sinked current (3.6 milliamps) flows from thesecond terminator to the LVD driver 180.

As stated above, substantially no differential current flows through thethird resistor 136. Accordingly, the first voltage source 146respectively impresses a center voltage of 1.25 volts on the node 138,and the LVD driver 180 causes a 3.6 milliamp) current to flow througheach of the first and the second resistors 132 and 134. Since a 3.6milliamp current is flowing from the first bus line 124 to the secondbus line 126, the voltage generated across the first resistor 132 raisesthe center voltage by 198 millivolts (3.6 milliamps×55 ohms), thusresulting in a first voltage of 1.448 (1.25 volts+198 millivolts) beingimpressed on the first bus line 124. Conversely, the voltage generatedacross the second resistor 134 lowers the center voltage by 198millivolts (3.6 milliamps×55 ohms), thus resulting in a second voltageof 1.052 volts (1.25 volts-198 millivolts) being impressed on the secondbus line 126. As a result of the above, a first differential voltage of+396 millivolts (1.448 volts-1.052 volts) is impressed upon thedifferential data line 122. In response to the +396 millivoltdifferential voltage, a LVD receiver (not shown) generates an outputsignal that is representative of the +396 millivolt differentialvoltage. A bus controller circuit then determines from this outputsignal that a binary zero is being transferred on the differential dataline 122.

As can be seen from the above description, the LVD driver 180 of thepresent invention was able to utilize substantially symmetrical currentsin order generate the substantially symmetrical differential voltages ofthe asserted and negated states. What is meant herein by symmetricalcurrents is two currents that have substantially equal magnitudes andopposite polarities. For example, the above LVD driver 180 applied afirst current of -7.2 milliamps to the first bus line 24 during theasserted state and applied a second current of +7.2 milliamps to thefirst bus line 24 during the negated state. The first current and thesecond current had substantially equal magnitudes (7.2 and 7.2 milliampsrespectively) and opposite polarities (negative and positive polarityrespectively). What is meant herein by symmetrical differential voltagesare two differential voltages that have substantially equal magnitudesand opposite polarities. For example, the above LVD driver 180 caused afirst differential voltage of -396 millivolts to be impressed on thedifferential data line 122 during the asserted state, and caused asecond differential voltage of +396 millivolts to be impressed on thedifferential data line 122 during the negated state. The firstdifferential voltage and the second differential voltage hadsubstantially equal magnitudes (396 and 396 millivolts respectively) andopposite polarities (negative and positive polarities respectively). Itshould be noted while the above examples illustrated exactly symmetricalcurrents producing exactly symmetrical voltages, due to variances incomponents, in practice the symmetrical currents will have slightlydifferent magnitudes and the symmetrical differential voltages will haveslightly different magnitudes. As a result, the above were described asbeing substantially symmetrical.

As can be seen from the above description, the SCSI bus configuration110 of the present invention resolves the problems associated withasymmetrical current driving. By removing the differential biasingvoltage prior to data transfer, the LVD driver 180 may generatesubstantially symmetrical currents in order to generate substantiallysymmetrical differential voltages for the asserted and negated states.As a result of this symmetrical current driving, the SCSI busconfiguration 110 enables data transfer at higher rates due to reducingthe noise associated with asymmetrical current driving. It should alsobe noted that by removing the differential biasing voltage during datatransfer the SCSI bus configuration 110 of the present inventionaddresses the problems associated with the differential biasing voltageswamping out the differential data signals during high transfer rates.

Furthermore, as may be seen from the above discussion, the SCSI busconfiguration 110 of the present invention enables terminators at eachend of the bus to provide substantially matched differential biasingvoltages without costly laser trimming of resistors. In particular, thecontrollable biasing circuit 140 allows for programmable adjustment ofthe differential biasing voltage supplied by the terminator. Thisprogrammable adjustment reduces the manufacturing cost of the LVDterminators because the components of the LVD terminators need not be sotightly matched since the differential biasing voltage provided by theLVD terminator may later be programmed. Furthermore, it should be notedthat this programmable adjustment also helps reduce loop currents thatmay be misinterpreted as data transfer.

Shown in FIG. 5 is a schematic diagram of a preferred embodiment for thefirst controllable current source 142. The first controllable currentsource 142 includes a control register 502, a reference current source510, mirrored current sources 520₁, 520₂, . . . 520_(N), and switches530₁, 530₂, . . . 530_(N). The reference current source 510 includes areference P-channel metal oxide semiconductor field effect transistor(MOSFET) M_(REF) and a reference resistor R_(REF). The referenceresistor R_(REF) couples the gate and the drain of the reference MOSFETM_(REF) to a low voltage source V_(SS) such as ground. Furthermore, thesource of the reference MOSFET M_(REF) is coupled to a high voltagesource V_(DD) such as 3.3 volts. The reference resistor R_(REF) controlsthe magnitude of the reference current I_(REF) which flows through thereference MOSFET M_(REF). In particular, the greater the resistance ofthe reference resistor R_(REF) the smaller the magnitude of thereference current I_(REF). The exact resistance of the referenceresistor R_(REF) will be dependent upon the electrical characteristicsof the reference MOSFET M_(REF) and the desired magnitude of thereference current I_(REF). In the preferred embodiment, the resistancethe reference resistor R_(REF) is set such that the reference currentI_(REF) is substantially equal to 100 microamps.

Each mirrored current source 520₁, 520₂, . . . 520_(N) is operable togenerate a current that is substantially equal to the reference currentI_(REF) produced by the reference current source 510. To this end, eachmirrored current source 520₁, 520₂, . . . 520_(N) includes a singleP-channel MOSFET M₁, M₂, . . . M_(N) respectively. Each gate of theMOSFETs M₁, M₂, . . . M_(N) is coupled to the gate of the referenceMOSFET M_(REF). Furthermore, each source of the MOSFETs M₁, M₂, . . .M_(N) is coupled to the high voltage source V_(DD). Furthermore, eachMOSFET M₁, M₂, M_(N) are matched devices that have electricalcharacteristics substantially equal to the electrical characteristics ofthe reference MOSFET M_(REF). As a result of the above interconnectionsand matched characteristics, each of the MOSFETs M₁, M₂, . . . M_(N)generates a current I₁, I₂, . . . I_(N) that is substantially equal toI_(REF). Since in the preferred embodiment I_(REF) is equal to 100microamps, each of the MOSFETs M₁, M₂, . . . M_(N) generates a currentI₁, I₂, . . . I_(N) that is substantially equal to 100 microamps.

Each switch 530₁, 530₂, . . . 530_(N) is operable to couple itsrespective mirrored current source 520₁, 520₂, . . . 520_(N) to theoutput I_(BIAS) based upon the status of a control signal received fromthe control register 502. To this end, each switch 530₁, 530₂, . . .530_(N) includes a single P-channel MOSFET M_(S).sbsb.1, M_(S).sbsb.2, .. . M_(S).sbsb.N, respectively. Each source of the MOSFETs M_(S).sbsb.1,M_(S).sbsb.2, . . . M_(S).sbsb.N is coupled to a respective gate of theMOSFETs M₁, M₂, . . . M_(N) and each gate of the MOSFETs M_(S).sbsb.1,M_(S).sbsb.2, . . . M_(S).sbsb.N is coupled to a respective output ofthe control register 502. Furthermore, each drain of the MOSFETsM_(S).sbsb.1, M_(S).sbsb.2 . . . M_(S).sbsb.N is coupled to the outputI_(BIAS) of the first controllable current source 142. Due to thisinterconnection scheme, if the control register 502 provides a switch530_(X) with a low voltage level (e.g. a V_(SS) of 0 volts), then theswitch 530_(X) will couple its respective mirrored current source520_(X) to the output I_(BIAS). However, if the control register 502provides the switch 530_(X) with a high voltage level (e.g. a V_(DD) of3.3 volts), then the switch 530_(X) will decouple its respectivemirrored current source 520_(X) from the output I_(BIAS).

The control register 502 is coupled to the switches 530₁, 530₂, . . .530_(N) and to the biasing control circuit 160. The control register 502is operable to receive a first biasing control signal from the biasingcontrol circuit 160 and to provide the switches 530₁, 530₂, . . .530_(N) with control signals. In one embodiment, the control register502 receives and stores a first biasing control signal that isrepresentative of a binary string. The control register 502 thenactivates the switches 530₁, 530₂, . . . 530_(N) corresponding to 1's inthe binary string and deactivates the switches 530₁, 530₂, . . . 530_(N)corresponding to 0's in the binary string.

In another embodiment, the control register 502 is implemented with acounter. In this embodiment, the control register 502 receives a firstbiasing control signal from the biasing control circuit 160 thatindicates either to increment or decrement the counter. The controlregister 502 then activates or deactivates switches 530₁, 530₂, . . .530_(N) in order to have a number of activated switches 530₁, 530₂, . .. 530_(N) equal to the value stored in the counter. It should be notedby activating and deactivating switches 530₁, 530₂, . . . 530_(N), thecontrol register 502 is able to control the amount of current producedby the first controllable current source 142. For example, assuming thateach mirrored current source 520₁, 520₂, . . . 520_(N) produces 100microamps, the control register may activate switches 530₁, . . . 530₅in order to produce a 500 microamp current. Therefore, if the firstcontrollable current source 142 has sixteen switches and sixteenmirrored current sources producing 100 microamps a piece, then the firstcontrollable current source 142 may generate currents from 0 to 1.6milliamps with a 100 microamp resolution.

It should be noted that generating mirrored currents that are a power oftwo larger than the reference current is relatively easy and inexpensiveto implement in integrated circuit manufacturing. As a result, inanother embodiment of the present invention each of the mirrored currentsources 520₁, 520₂, . . . 520_(N) generates a current I₁, I₂, . . .I_(N) that is a power of two larger than the reference current I_(REF).For example, assuming that I_(REF) is equal to 100 microamps and thatthe first controllable current source 142 includes four switches 530₁ .. . 530₄ and four mirrored current sources 520₁ . . . 520₄, then thefirst mirrored current source 520₁ produces 100 microamps (2⁰ ×I_(REF)),the second mirrored current source 520₂ produces 200 microamps (2¹×I_(REF)), the third mirrored current source 520₃ produces 400 microamps(2² ×I_(REF)), and the fourth mirrored current source 520₄ produces 800microamps (2⁴ ×I_(REF)) As a result of this configuration, the firstcontrollable current source is capable of generating a biasing currentI_(BIAS) from 0 to 1.5 milliamps with a 100 microamp resolution. Forexample, the control register 502 could activate the second switch 530₂and the fourth switch 530₄ in order to produce a biasing currentI_(BIAS) of 1.0 milliamps.

Shown in FIG. 6 is a schematic diagram of a preferred embodiment for thesecond controllable current source 144. The second controllable currentsource 144 includes a control register 602, a reference current source610, mirrored current sources 620₁, 620₂, . . . 620_(N), and switches630₁, 630₂, . . . 630_(N) The operation and structure of the secondcontrollable current source 144 is nearly identical to the operation andstructure of the first controllable current source 142. The maindifference is that the P-channel MOSFETs of the first controllablecurrent source 142 are replaced with N-channel MOSFETs in the secondcontrollable current source 144. Furthermore, the low voltage source andthe high voltage source connections of the first controllable currentsource 142 are swapped in the second controllable current source 144.Since the structure and operation of the second controllable currentsource 144 would be understood by one skilled in the art from the abovedescription of the first controllable current source 142 and the FIGS. 5and 6, the second controllable current source 144 is not discussed infurther detail.

Referring back to FIG. 2, the LVD terminator 115, the LVD driver 180, aLVD receiver (not shown), and the bus controller circuit 190 areimplemented in a single integrated circuit chip in a preferredembodiment. In order to clearly define what is meant by a singleintegrated circuit chip reference is made to FIG. 7. In FIG. 7, a singleintegrated circuit chip 700 is illustrated. The single integratedcircuit chip 700 includes an integrated circuit package 710 and anintegrated circuit substrate 720. The package 710 is typicallyimplemented with ceramics or other insulator materials. Furthermore, thepackage 710 includes terminals or pins 712. The terminals 712 areconductors which provide external contacts for transferring signals intoand out of integrated circuit chip 700. Moreover, the package 710mechanically supports the substrate 720 during operation of theintegrated circuit chip 700.

The substrate 720 is a single wafer made of a semiconductor materialsuch as silicon (Si) or gallium arsenate (GaAs). The LVD terminator 115,the LVD driver 180, the LVD receiver, and the bus controller circuit 190are implemented on the semiconductor using known integrated circuitmanufacturing techniques such as doping. The substrate 720 includesinput/output (I/O) pads 722 which provide a relatively large (ascompared to the size of the transistors doped in the substrate 720)conductor contact to the integrated circuit implemented in the substrate720. Bonding wires 724 couple the I/O pads 722 to the terminals 712. Thecombination of the terminals 712, the bonding wires 724, and the I/Opads 722 provide a mechanism for transferring signals to and from theoutside of the integrated circuit chip 700 to the LVD terminator 115,the LVD driver 180, the LVD receiver, and the bus controller circuit 190that are implemented in the substrate 720.

It should be noted that recent integrated circuit chips such as thePentium Pro processor implemented by Intel, Corporation of Santa Cruz,Calif. have utilized a combination of more than one substrate within asingle integrated circuit chip. In these implementations, bonding wireswithin the integrated circuit chip electrically couple the substratestogether within the integrated circuit chip. Thus, it should beappreciated that the substrate 720 of integrated circuit chip 700 may bemade up of more than one individual semiconductor wafer. For example,the integrated circuit chip may include a first semiconductor wafer anda second semiconductor wafer which (i) are interconnected by a number ofbonding wires, and (ii) are supported by the package 710. In thisembodiment, the first semiconductor wafer and the second semiconductorwafer may collectively have the LVD terminator 115, the LVD driver 180,the LVD receiver, and the bus controller circuit 190 fabricated thereon.

Moreover, it should be rioted that a single integrated circuit chip isnot made up individual circuit components that have been mounted to acircuit board with various wires and traces interconnecting the circuitcomponents. For example, multiple integrated circuit chips which areinterconnected by various wires and traces, when take together, do notmake up a single integrated circuit chip. Additionally, an integratedcircuit chip that is interconnected to discrete components (e.g.resistors and transistors) by various wires and traces do not, when taketogether, make up a single integrated circuit chip.

Furthermore, it should be noted that the programmability of the biasingvoltage of the present invention has enabled the cost effectiveintegration of the LVD terminator and bus controller circuit into asingle integrated circuit package. Prior to the present invention,combining the LVD terminator with the bus controller circuit in a singleintegrated circuit chip was not done due to the high manufacturing costsassociated with the prior art LVD terminators. However, theprogrammability of the biasing voltage of the present invention allowsfor cheaper manufacturing processes to be used to implement the LVDterminator. As a result, combination of the LVD terminator 115 of thepresent invention with the bus controller circuit 190 in a singleintegrate circuit chip provides a full-featured and low cost integratedcircuit chip that was not achievable from the prior art LVD terminators.

While the invention has been illustrated and described in detail in thedrawings and foregoing description, such illustration and description isto be considered as exemplary and not restrictive in character, it beingunderstood that only the preferred embodiment has been shown anddescribed and that all changes and modifications that come within thespirit of the invention are desired to be protected.

What is claimed is:
 1. A method of transferring data across a differential data line having a first bus line and a second bus line, comprising the steps of:developing a differential biasing voltage between said first bus line of said differential data line and said second bus line of said differential data line; removing said differential biasing voltage from said first bus line and said second bus line; and transferring data across said differential data line after said removing step.
 2. The method of claim 1, wherein said transferring step includes the steps of:generating a first differential voltage between said first bus line and said second bus line in order to transfer a binary one, and generating a second differential voltage between said first bus line and said second bus line in order to transfer a binary zero, said first differential voltage and said second differential voltage having substantially equal magnitudes and opposite polarities.
 3. The method of claim 1, wherein said transferring step includes the steps of:generating a first current that produces a first differential voltage between said first bus line and said second bus line in order to transfer a binary one, and generating a second current that produces a second differential voltage between said first bus line and said second bus line in order to transfer a binary zero, said first differential voltage and said second differential voltage having substantially equal magnitudes and opposite polarities, and said first current and said second current having substantially equal magnitudes and opposite polarities.
 4. The method of claim 1, wherein:said developing step includes the steps of (i) impressing a first biasing voltage upon said first bus line, and (ii) impressing a second biasing voltage upon said second bus line, said differential biasing voltage being a voltage difference between said first biasing voltage and said second biasing voltage, and said removing step includes the steps of (i) removing said first biasing voltage from said first bus line, and (ii) removing said second biasing voltage from said second bus line.
 5. The method of claim 1, wherein:said developing step includes the steps of (i) coupling a first current to a first resistor to impress a first biasing voltage upon said first bus line, and (ii) coupling a second current to a second resistor to impress a second biasing voltage upon said second bus line, said differential biasing voltage being a voltage difference between said first biasing voltage and said second biasing voltage, and said removing step includes the steps of (i) decoupling said first current from said first resistor to remove said first biasing voltage from said first bus line, and (ii) decoupling said second current from said second resistor to remove said second biasing voltage from said second bus line.
 6. The method of claim 1, wherein said removing step includes the steps of:generating a control signal upon determining that said data is to be transferred across said differential data line, and decoupling said differential biasing voltage from said differential data line in response to generation of said control signal.
 7. The method of claim 1, wherein said removing step includes the steps of:generating a control signal upon determining that said data is to be transferred across said differential data line, decoupling a first current from a first resistor to remove a first portion of said differential biasing voltage from said differential data line in response to generation of said control signal, and decoupling a second current from a second resistor to remove a second portion of said differential biasing voltage from said differential data line in response to generation of said control signal.
 8. A terminator that provides a differential biasing voltage for a differential data line having a first bus line and a second bus line, comprising:an impedance network coupled to said first bus line and said second bus line, said impedance network configured to substantially match a characteristic impedance of said differential data line; and a controllable biasing circuit having a control input configured to receive a control signal, said controllable biasing circuit being coupled to said differential data line and configured to (i) develop said differential biasing voltage between said first bus line and said second bus line, and (ii) remove said differential biasing voltage from said differential data line based upon said control signal.
 9. The terminator of claim 8, wherein:said controllable biasing circuit is further configured to (i) impress a first biasing voltage upon said first bus line, (ii) impress a second biasing voltage upon said second bus line, (iii) remove said first biasing voltage from said first , bus line in response to said control signal, and (iv) remove said second biasing voltage from said second bus line in response to said control signal.
 10. The terminator of claim 8, wherein:said impedance network includes a first resistor coupled to said first bus line and a second resistor coupled to said second bus line, said first resistor and said second resistor in combination has an impedance substantially equal to a characteristic impedance of said differential data line, said controllable biasing circuit includes a first switch, a second switch, a first current source, and a second current source, said first switch is coupled between said first current source and said first resistor and configured to selectively couple a first current generated by said first current source to said first resistor based upon said control signal, and said second switch is coupled between said second current source and said second resistor and configured to selectively couple a second current generated by said second current source to said second resistor based upon said control signal.
 11. A bus interface for controlling a differential bus having a differential data line that includes a first bus line and a second bus line, comprising:a bus controller circuit coupled to said differential bus and configured to (i) control transfer of data across said differential bus, and (ii) generate a biasing control signal prior to data transfer on said differential data line; an impedance network coupled to said first bus line and said second bus line, said impedance network configured to substantially match a characteristic impedance of said differential data line; and a controllable biasing circuit coupled to said differential data line and configured to (i) develop a differential biasing voltage between said first bus line and said second bus line, and (ii) remove said differential biasing voltage from said differential data line in response to said biasing control signal.
 12. The bus interface of claim 11, wherein:said bus controller circuit includes a bus driver coupled to said differential data line, said bus driver is configured to (i) generate a first differential voltage between said first bus line and said second bus line in response to a first control signal to transfer a binary one, and (ii) generate a second differential voltage between said first bus line and said second bus line in response to a second control signal to transfer a binary zero, and said bus driver is further configured to generate said first differential voltage and said second differential voltage such that said first differential voltage and said second differential voltage have substantially equal magnitudes and opposite polarities.
 13. The bus interface of claim 11, wherein:said bus control circuit includes a bus driver having a first current source and a second current source that are coupled to said impedance network, said first current source is configured to generate a first current through said impedance network in order to impress a first differential voltage between said first bus line and said second bus line, said first current source being configured to generate said first current in response to a first signal to transfer a binary one on said differential data line, said second current source is configured to generate a second current through said impedance network in order to impress a second differential voltage between said first bus line and said second bus line, said second current source being configured to generate said second current in response to a second signal to transfer a binary zero on said differential bus line, said first current source and said second current source are further configured to generate said first current and said second current such that said first current and said second current have substantially equal magnitudes and opposite polarities, and said impedance network is configured such that said first current and said second current cause said impedance network to impress said first differential voltage and said second differential voltage between said first bus line and said second bus line such that said first differential voltage and said second differential voltage have substantially equal magnitudes and opposite polarities.
 14. The bus interface of claim 11, wherein:said controllable biasing circuit is further configured to (i) impress a first biasing voltage upon said first bus line, (ii) impress a second biasing voltage upon said second bus line, (iii) remove said first biasing voltage from said first bus line in response to said biasing control signal, and (iv) remove said second biasing voltage from said second bus line in response to said biasing control signal.
 15. The bus interface of claim 11, wherein:said impedance network includes a first resistor coupled to said first bus line and a second resistor coupled to said second bus line, said first resistor and said second resistor in combination has an impedance substantially equal to a characteristic impedance of said differential data line, said controllable biasing circuit includes a first switch, a second switch, a first current source, and a second current source, said first switch is coupled between said first current source and said first resistor and is configured to (i) couple a first current generated by said first current source to said first resistor and (ii) decouple said first current from said first resistor in response to said biasing control signal, and said second switch is coupled between said second current source and said second resistor and is configured to (i) couple a second current generated by said second current source to said second resistor and (ii) decouple said second current from said second resistor in response to said biasing control signal. 